1. Technical Field
Generally, this invention relates to semiconductor processing using photosensitive materials on a substrate. More particularly, it relates to a method of providing a metal interconnecting wiring layer which is self-aligned to an underlying contact window.
2. Background Art
There is a continuing effort in the semiconductor industry to devise new methods of increasing the circuit density of VLSI devices to increase the speed and performance of microprocessors. The devices fabricated on a semiconductor chip are typically interconnected by a number of conductive metal layers separated from each other by dielectric material. These metal layers are connected to each other and to the underlying devices either by vias, or contact windows, which are holes in the dielectric which allow an upper conductive layer to descend through the dielectric to make electrical contact with a lower layer. Another common approach to interconnect the metal layers is by the use of separate stud layers of conductive material. The requirement to maintain a sufficient contact area between the metal layer and the contact window or stud level necessitates an increase in the dimensions of the various features in the metal and window, or stud layers, to compensate for overlay errors and process bias inherent in lithographic processes. This increase in the size of the design ground rules results in a significant loss in circuit layout density. In addition, millions of dollars are spent annually on photolithographic equipment and processes to make improvements in overlay error and process bias. To minimize the chip area devoted to overlay tolerance and lithography costs, many "self-aligned" processes have been developed by process engineers.
In addition to the loss of chip area due to overlay tolerances, there are many problems in manufacturing stud layers and contact windows at the dimensions which the semiconductor industry is developing for the next generation of integrated circuits. In the prior art, the metal stud level is typically formed by a lift-off process. At dimensions of 1.5 microns or less, it becomes increasingly difficult to assure good adhesion of the metal stud to the metal layer on which it is situated. Therefore, the metal studs have a tendency to be removed with the rest of the lift-off layer, thus creating an open circuit. Where contact windows are etched into a dielectric layer, the sides of the contact windows must be sloped to guarantee good continuity of the metal layer as it descends into the contact window. The steeper the slope, the more likely it is the metallurgy will have breaks at the edges of the contact windows. However, the use of a gradually sloped sidewall to guarantee metal line continuity takes up valuable chip area and prevents contact windows from being packed as closely as desired. In addition, the use of contact windows creates a very irregular surface which makes subsequent interconnecting layers much more difficult to reliably fabricate.
One prior art method discussed in commonly assigned U.S. Pat. No. 4,789,648 to Chow, et al. was developed to address some of these concerns. In this method, a compound dielectric layer is deposited over a first layer of patterned conductive material. The compound dielectric layer consists of an etch stop layer patterned with contact holes sandwiched between two dielectric layers of a material such as silicon dioxide. A second photoresist layer is applied and patterned to define the upper level interconnecting layer. The upper layer of dielectric is then etched to the etch stop layer to form wiring channels. In those locations where the contact holes are exposed, the etching continues to form vertically sided contact windows which extend to the first layer of patterned conductive material. The channels and contact windows are filled with a metal layer, and the excess metal is removed by etching or by chemical-mechanical polishing.
While this process overcomes many of the deficiencies of the prior art, it is not a self-aligned process. Therefore, additional chip area is required to allow for overlay errors and processes bias. Two separate photolithography steps are required to form the contact holes and the wiring channels adding to the total lithographic tool count and process time required to manufacture the integrated circuit. Also, the process is designed specifically for fabricating metallurgy layers on existing metal layers, it does not provide for depositing metallurgy layers directly on semiconductor device.